×

Happy to Help!

This website doesn't store cookies. Enjoy the experience, without worrying about your data!

Great, thanks!

Test Vector Wrapper for LTE-PHY Test bed

Project brief:
  • To design, develop and implement a strategy to load, test analyze the test vectors to and from the Signal-Chain of an LTE-PHY framework
Project description & features:
  • Implemented in Altera – Startix II GX device, in VHDL
  • Use of High Speed DDR2 Memory controller to store the test vectors
  • 32-Bit Cluster Bus I/F Logic with Avalon bus interface
  • Firmware for GX-AMC card in a u-TCA Chassis environment.
  • Configuration using command messaging
  • System testing on the LTE-PHY
  • test bed hardware
Domain:
  • Telecom
Tools & technology:
  • Quartus II, Signal Tap Logic Analyzer
  • Model Sim, MATLAB, Cadence Allegro.
Contact Us

© 2018 Embitel. All Rights Reserved